The present invention relates to a data cell transmission apparatus. More particularly, the invention relates to an apparatus for transmitting data cells of constant bit rates.
In the conventional art of the field, various apparatuses for transmitting constant bit rate (CBR) data cells to an asynchronous transfer mode (ATM) network have been invented.
For example, a technology has conventionally been presented to realize an adapter chip adapted to interface a variety of constant bit rate services to a central buffer data bus.
As another example, a CDV control method for CBR traffic has been presented. The CDV control method performs control in such a way as to limit cell delay fluctuation to a minimum, which occurs during passing through the ATM network, by providing a shaping FIFO in an output stage from an ATM switch to a terminal and storing a group of input CBR cells for a predetermined period of time.
However, in any of the foregoing technologies, no consideration is given to a case where concentration of accessing occurs in the data bus, causing a high load state thereof, when a number of data cells are transmitted. Head data cells need more time than data cells other than the head data cells to be processed. Therefore, if the head data cells are sent out through adjacent slots continuously, it causes that constant bit rates cannot be maintained. As a result, there is always a possibility that constant bit rates cannot be maintained because of the temporary high load state of the data bus.